US Patent Class 710
ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT




Electronic
File
Wrappers


Electronic
Patent
Documents


Paper
Patent
Documents

Current as of: June, 1999
Click for Main Headings
Click DF for Definitions
Click for All Classes

Internet Version by PATENTEC © 1999       Terms of Use



Products
and
Services


  DF  CLASS NOTES
1  DF  INPUT/OUTPUT DATA PROCESSING
2  DF  .~ Input/Output expansion
3  DF  .~ Input/Output addressing
4  DF  .~.~ Address data transfer
5  DF  .~ Input/Output command process
6  DF  .~.~ Operation scheduling
7  DF  .~.~ Concurrently performing Input/Output operation and other operation unrelated to Input/Output
8  DF  .~ Peripheral configuration
9  DF  .~.~ Address assignment
10  DF  .~.~ Configuration initialization
11  DF  .~.~ Protocol selection
12  DF  .~.~ As input or output
13  DF  .~.~ By detachable memory
14  DF  .~.~ Mode selection
15  DF  .~ Peripheral monitoring
16  DF  .~.~ Characteristic discrimination
17  DF  .~.~ Availability monitoring
18  DF  .~.~ Activity monitoring
19  DF  .~.~ Status updating
20  DF  .~ Concurrent Input/Output processing and data transfer
21  DF  .~.~ Concurrent data transferring
22  DF  .~ Direct Memory Accessing (DMA)
23  DF  .~.~ Programmed control memory accessing
24  DF  .~.~ By command chaining
25  DF  .~.~ Timing
26  DF  .~.~ Using addressing
27  DF  .~.~ Via separate bus
28  DF  .~.~ With access regulating
29  DF  .~ Flow controlling
30  DF  .~ Frame forming
31  DF  .~ Transfer direction selection
32  DF  .~ Transfer termination
33  DF  .~ Data transfer specifying
34  DF  .~.~ Transferred data counting
35  DF  .~.~ Burst data transfer
36  DF  .~ Input/Output access regulation
37  DF  .~.~ Access dedication
38  DF  .~.~ Path selection
39  DF  .~.~ Access request queuing
40  DF  .~.~ Access prioritization
41  DF  .~.~.~ Dynamic
42  DF  .~.~.~ Group
43  DF  .~.~.~ Physical position
44  DF  .~.~.~ Prioritized polling
45  DF  .~.~.~ Time-slot accessing
46  DF  .~.~ Input/Output polling
47  DF  .~.~.~ Polled interrupt
48  DF  .~.~ Input/Output interrupting
49  DF  .~.~.~ Masking
50  DF  .~.~.~ Vectored
51  DF  .~.~ Accessing via a multiplexer
52  DF  .~ Input/Output data buffering
53  DF  .~.~ Alternately filling or emptying buffers
54  DF  .~.~ Queue content modification
55  DF  .~.~ Contents validation
56  DF  .~.~ Buffer space allocation or deallocation
57  DF  .~.~ Fullness indication
58  DF  .~ Input/Output process timing
59  DF  .~.~ Processing suspension
60  DF  .~.~ Transfer rate regulation
61  DF  .~.~ Synchronous data transfer
62  DF  .~ Peripheral adapting
63  DF  .~.~ Universal
64  DF  .~.~ Via common units and peripheral-specific units
65  DF  .~.~ Input/Output data modification
66  DF  .~.~.~ Width conversion
67  DF  .~.~.~ Keystroke interpretation
68  DF  .~.~.~ Data compression and expansion
69  DF  .~.~.~ Analog-to-digital or digital-to-analog
70  DF  .~.~.~ Digital-to-digital
71  DF  .~.~.~ Serial-to-parallel or parallel-to-serial
72  DF  .~.~ Application-specific peripheral adapting
73  DF  .~.~.~ For user input device
74  DF  .~.~.~ For data storage device
100  DF  INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)
101  DF  .~ Bus expansion or extension
102  DF  .~.~ Card insertion
103  DF  .~.~.~ Hot insertion
104  DF  .~ System configuring
105  DF  .~ Protocol
106  DF  .~.~ Using transmitter and receiver
107  DF  .~ Bus access regulation
108  DF  .~.~ Bus locking
109  DF  .~.~ Bus polling
110  DF  .~.~ Bus master/slave controlling
111  DF  .~.~ Rotational prioritizing (i.e., round robin)
112  DF  .~.~ Bus request queuing
113  DF  .~.~ Centralized bus arbitration
114  DF  .~.~.~ Static bus prioritization
115  DF  .~.~.~.~ Physical position bus prioritization
116  DF  .~.~.~ Dynamic bus prioritization
117  DF  .~.~.~ Time-slotted bus accessing
118  DF  .~.~.~ Delay reduction
119  DF  .~.~ Decentralized bus arbitration
120  DF  .~.~.~ Hierarchical or multilevel accessing
121  DF  .~.~.~ Static bus prioritization
122  DF  .~.~.~.~ Physical position bus prioritization
123  DF  .~.~.~ Dynamic bus prioritization
124  DF  .~.~.~ Time-slotted bus accessing
125  DF  .~.~.~ Delay reduction
126  DF  .~ Bus architecture
127  DF  .~.~ Buses having variable widths
128  DF  .~.~ Dual bus system
129  DF  .~ Interface architecture
130  DF  .~.~ Using register structure
131  DF  .~ Switching (i.e., intrasystem connection path selecting)
132  DF  .~.~ Crossbar
200  DF  ACCESS LOCKING
220  DF  ACCESS POLLING
240  DF  ACCESS ARBITRATING
241  DF  .~ Centralized arbitrating
242  DF  .~ Decentralized arbitrating
243  DF  .~ Hierarchical or multilevel arbitrating
244  DF  .~ Access prioritizing
260  DF  INTERRUPT PROCESSING
261  DF  .~ Multimode interrupt processing
262  DF  .~ Interrupt inhibiting or masking
263  DF  .~ Interrupt queuing
264  DF  .~ Interrupt prioritizing
265  DF  .~.~ Variable
266  DF  .~ Programmable interrupt processing
267  DF  .~ Processor status
268  DF  .~ Source or destination identifier
269  DF  .~ Handling vector