US PATENT SUBCLASS 257 / 503
.~ With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)

Current as of: June, 1999
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257 /   HD   ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)

499  DF  INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS {9}
503.~ With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit)

DEFINITION

Classification: 257/503

With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit):

(under subclass 499) Subject matter wherein the chip includes contacts or electrical interconnections, such as metal strips deposited on the surface of the chip, which contacts or interconnections are configured in such a manner as to reduce or eliminate unwanted parasitic coupling of electrical signals from one part or component of the integrated circuit to another.

(1) Note. Such configuration might be, for example, a shielding conductive layer connected to fixed potential, or large area metal pads for connection to external supply voltages with plural separate pads provided to connect different parts or components of the same integrated circuit to the same external voltage, to prevent voltage drops from electrical current flowing between a pad and one component from producing a parasitic varying voltage applied to another component.

SEE OR SEARCH THIS CLASS, SUBCLASS:

659, for electrical shielding, in general, in active solid-state devices.

664, for transmission line connections, in general, in active solid-state devices.