US PATENT SUBCLASS 326 / 94
.~ Metastable state prevention

Current as of: June, 1999
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326 /   HD   ELECTRONIC DIGITAL LOGIC CIRCUITRY

93  DF  CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES {2}
94.~ Metastable state prevention

DEFINITION

Classification: 326/94

Metastable state prevention:

(under subclass 93) Subject matter including a circuit to prevent the occurrence of an undecided condition at a logic state transition.

(1) Note. A metastable state can occur when a logic voltage output level is between the logic 0 and logic 1 levels.

SEE OR SEARCH CLASS

327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems,

198+, for initializing, resetting or protecting a steady state condition of a stable state circuit such as a flip-flop.