US PATENT SUBCLASS 438 / FOR 202
.~.~.~.~ Gate structure constructed of diverse dielectrics (437/42)


Current as of: June, 1999
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438 /   HD   SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

FOR 149  DF  INCLUDING FORMING A SEMICONDUCTOR JUNCTION (437/15) {7}
FOR 150  DF  .~ Using energy beam to introduce dopant or modify dopant distribution (437/ 16) {5}
FOR 155  DF  .~.~ Of semiconductor on insulating substrate (437/21) {14}
FOR 173  DF  .~.~.~ Involving Schottky contact formation (437/39) {12}
FOR 202.~.~.~.~ Gate structure constructed of diverse dielectrics (437/42) {20}
FOR 203  DF  .~.~.~.~.~> Gate surrounded by dielectric layer, e.g., floating gate, etc. (437/43)
FOR 204  DF  .~.~.~.~.~> Adjusting channel dimension (437/44)
FOR 205  DF  .~.~.~.~.~> Active step for controlling threshold voltage (437/45)
FOR 185  DF  .~.~.~.~.~> Self-aligned (437/41 R)
FOR 186  DD  .~.~.~.~.~> With bipolar (437/41 RBP)
FOR 187  DD  .~.~.~.~.~> CMOS (437/41 RCM)
FOR 188  DD  .~.~.~.~.~> Lightly doped drain (437/41 RLD)
FOR 189  DD  .~.~.~.~.~> Memory devices (437/41 RMM)
FOR 190  DD  .~.~.~.~.~> Asymmetrical FET (437/41 AS)
FOR 191  DD  .~.~.~.~.~> Channel specifics (437/41 CS)
FOR 192  DD  .~.~.~.~.~> DMOS/vertical FET (437/41 DM)
FOR 193  DD  .~.~.~.~.~> Gate specifics (437/41 GS)
FOR 194  DD  .~.~.~.~.~> Junction FET/static induction transistor (437/41 JF)
FOR 195  DD  .~.~.~.~.~> Layered channel (437/41 LC)
FOR 196  DD  .~.~.~.~.~> Specifics of metallization/contact (437/41 SM)
FOR 197  DD  .~.~.~.~.~> Recessed gate (Schottky falls below in SH) (437/41 RG)
FOR 198  DD  .~.~.~.~.~> Schottky gate/MESFET (437/41 SH)
FOR 199  DD  .~.~.~.~.~> Sidewall (437/41 SW)
FOR 200  DD  .~.~.~.~.~> Thin film transistor, inverted (437/41 TFI)
FOR 201  DD  .~.~.~.~.~> Thin film transistor (437/41 TFT)


DEFINITION

Classification: 438/FOR.202

Gate structure constructed of diverse dielectrics:

Foreign art collection for processes wherein the gate structure is made from different dielectric materials.